~ analog w devices i features functionally complete: includes instrumentation amplifier, sample/hold amplifier, and analog to digital converter differential nonlinearity: :to.oo2% fsr max (das1156) guaranteed nonlinearity: :to.oo5% fsr (das1155) :to.oo3% fsr (da~1156) high common mode rejection: -bodb (up to 500hz) high feedthrough rejection: - 96db resistor programmable gain: 1vn to 1000vn byte selectable tri-state buffer outputs internal gain and offset potentiometers applications low level high accuracy data acquisition systems process control nuclear instrumentation automated test equipment medical instrumentation general description the oas1l55/oas1l56 are 14-/15-bit low level data acquisition systems having a minimum throughput rate of 25khz/20khz. these data acquisition systems provide high accuracy, high stability, and functional completeness all in a 2" x 4" x 0.44" metal case. guaranteed high accuracy system performance such as nonlinearity of ::,::0.005% fsr (oas1155)/::,::0.003% fsr (01\51156) and differential nonlinearity of ::,::0.003% fsr (oa51155)/::,::0.002% fsr (oasi156) are provided. guaranteed stability such as differential nonlinearity t.e. of ::':: 2ppm/oc maximum, offset t.e. of ::'::(1 + so/g) f-lv/oc (rti) and gain t.e. (rt!) of ::':: 16ppm/oc are also provided by the oas1155/oas1156. each oas1155/0as1156 makes extensive use of both integrated circuit and thin-film components to obtain its excellent perfor- ref ou'ro- 0 i ."olaa 0"'" l- ..ov r"'rene' g"n aoju.. i>' ",pu' ms3 ms. "" "'j .", "" '" , '" , 'hi "'ie 'u"'rs g"n- ("~)e "'" ." anawg <0 m""" cunv""r "" control '" , "" '" " '" " '" " "'" conver' com"ano 'hi .. '" 'u","' ." " "s. for oas"'" 8" " "s8 for oas""" anacog groun~ iana?'" . d'g>w grounds aaf connwed 'nlern"", olg"al gaouno ----------------- figure 1. das1155/das1156 block diagram - - 14-bit & 15-bit low level data acquisition systems das1155/das1156 i mance and small size. incorporated in these devices are a gain programmable instrumentation amplifier, precision sample/hold amplifier, high accuracy 14-/15-bit analog to digital converter, tri-state output buffers, gain and offset trim potentiometers, and power supply bypass capacitors (as shown in figure 1). unipolar coding is provided for true binary format with bipolar coding displayed in offset binary or two's complement. tri-state buffers are available for easy interface to bus structured applica- tions. operation the oasl155/0a51156 are designed, built, and tested to meet system data acquisition requirements. these units can significantly reduce design and debug time by providing, in one package, all of the circuitry necessary for low level data acquisition and microprocessor bus interface. for operation, the only connections necessary to the oas1155/ da51156 are the::,:: 15v and + 5v power supplies, analog input signal, trigger pulse, and the hi-enable/lo-enable tri-state controls. digital output programming is user selectable via external jumper connections. iii analog input section the analog input section consists of a true differential instru- mentation amplifier used to obtain high accuracy measurements in the presence of noise (as shown in figure 2). it also provides input impedance of (loom!!) and high common mode rejection of (- 80db). user selectable gain of ivn to 1o00vn via an external resistor enables either low level or high level full scale ranges to be applied to the input (+ lomv to + lov unipolar, ::':: smv to :: sv bipolar) with gain dctcrmincd by thc following formula: gai~ = i ... ( 20k ) r(, - - data acquisition su8ystea! yoi-.. '115-17 - -- obsolete
s pee i fie a t i 0 n s (typical @ + 25& and rated supplies unless otherwise noted) dasil55 dasil56 outline dimensions model resolution dynamiccharacteristics adcconversion time ja settling time, (jov output swing) too.oo3%fsr(itg~1 too.oo3% fsr in g= 10 too.oi% fsr in g = jooo throughput rate (a g= i, 10 14bi" 35fts max 15ftsmax 15ftsmax 50fts 25khz min 15 bits dimensions shown in inches and (mm). 44ft' max nconouctiv[ label 0.25 10" mln 20khz min 0.'" oia pin half.haro brass i- golo plateo imil-g"52041 3.800 ,..., sample hold acquisition time aperature delay time aperture uncertainty time feedthrough rejection i droop rate 4fts max sons ins - 96db 0.65ft vlfts 5fj.smax r metal case 1.30 1330:=::1 1-'" ";0-41 2.03 j .02110211 :t 0.oo2% max :to.003%max '5v dig. gro. msb ' msb b2 b3 .. b5 -h .. b7 .. b' b10 bl1 b12 b'3 ,'sv -15v ana. gro. . input - input bip ofs. ref out >++-i- ra accuracy differential nonlinearity (fsr)' integral nonlinearity (fsr)' no missing codes offset error gain error :to.oo3%max :to.oo5%max guaranteed adjustable to zero adjustable to zero sih control t+heoc .hi enable lo enable 'trig in.c. bit 14 ilsb' stability offset (rti)t.c. gain(rti)t.c. differential nonlinearity t .c. power supply sensitivity "'(i +~ftvf'c '" 16ppmf'c '" 2ppmf'c max :t 0.0015% fsr'i% vs --11--0.1125." grid top view 'fo, modo! oas"" - bi, 15 ilsbi "fo, modol oas".5 - b. 14 ilsbi interconnection and shielding techniques to preserve the high cmr characteristics of the dasllssidaslls6, care must be taken to minimize noise wherever possible. for best performance use twisted shielded cable, for the sensitive input signal, to reduce inductive and capacitive pickup. the cable should be connected as close as possible to the input common mode signal source. place the gain setting resistor as close as possible to its re- spective terminal connections to avoid pick- up. analog inputs ( adc fsr ) voltage input range ~ instrumentation amplifier gain gain range gain equation input impedance bias current offset current cmr (up to 5oohz\ cmv digitalinputs adc convert command' sha control low enable, high enable digital outputs parallel data outputs unipolar bipolar output drive status output drive + jomvto + jov(unipolar) :t 5mvto '" sv(bipolar) resistor programmable i to jooo g=i+(20kn) rg io'n 50na 2na - sodb ",jov i ttl load, positive pulse negative edge triggered hold = logic 0 sample = logic j enable = logico tri-state binary offset binary, 2's complement 2ttl loads logic" j" during conversion 2ttl loads internal reference voltage external load current (rated performance) temperature stability + jov, ",0.3% 2ma (max) :ts.5ppmf'c(max) power requirements rated voltages operating voltages' supply current drain :t 15v +5v temperature range specified operating storage relative humidity shielding ",j5v "'5%, +5v ",5% '" 12vro '" 17v, +4.75vto +5.2sv ",40ma soma oto+70c -25c to +s5c - 25c to + s5c (meets mil-std-202e, method 103b) electrostatic (rfi)6sides, electromagnet (emi) 5 sides size 2" x 4" x 0.44" metal package notes 'measured in hold mode, inpul 20v pk-pk @ 10khz. 'fsr means full sc.je range. 'wont,a.. summ"ion of la, s/h and aid nonlinearity errors. 'when connecting the convert command the s/h control tenninals tog applying the das1155/das1156 ref ou1 connec1 r- 'g';.:~7~~r : i ':;:~:: l- gain aojus1 '4- "8't a'" converter sih control figure 2. analog input block diagram the gain t.c., of the das1l55/das1l56, will be directly affected by the resistor used for rg' using a high quality metal film resistor is recommended. bipolar operation is obtained by connecting the ref out and the bipolar offset terminals together. the output of the instrumentation amplifier drives the sample/hold amplifier which has a gain of ivn. the sample/hold amplifier holds the input signal at a constant level during the a/d conversion. acquisition times of 4j.ls and 5j.ls maximum are provided re- spectively by the das1l55 and das1l56. full scale aid converter input range is programmed for + iov (unipolar) or:!: 5v (bipolar). therefore, the instrumentation amplifier gain must be set ac- cordingly to obtain maximum usable resolution. common mode rejection cmr is dependent on source impedance imbalance, signal fre- quency, and amplifier gain. cmr is specified having a :!: iov cmv and lkn source imbalance over a frequency range of dc to 500hz. figure 3 illustrates the typical cmr vs. source impedance 110 f = 60hz !g 90 ex: ::; 80 u ------ 70 .- - _u_~--_. 60 1k 10k source imbalance - " look figure 3. cmr vs gain and source imbalance das1155/ das1156 150 140 130 120 !g 110 , 100 ex: ::; 90 u bo 10 60 50 10' 10-' 10' 10' 10' f - hz figure 4. cmr vs frequency dasl155/dasl156 --- imbalance for the dasll55/dasil56. increasing the input gain of the instrumentation amplifier increases the cmr. at gain = ivn, cmr is maintained greater than 80db for source impedance imbalance up to !ok!!. figure 4 illustrates the cmr vs. gain and frequency. settling time vs. gain illustrated in figure 5 is the typical settling time vs. gain of the instrumentation amplifier in the das1155/das1156. settling times are specified to 0.003% fsr for gains i and 10, and to 0.01% fsr for gain to 1000 having an output step voltage of 10 volts. settling time to 0.003% fsr for gains greater than 10 are not shown because of the effects of voltage noise at the higher gains. 35 ";. 30 , 25 ~ " 20~ ---- '" ~ 15 :: ~ 10 ~- 5 1 10 100 gain - vn 1000 figure 5. typical settling time vs gain timing diagram the timing diagram for the dasil5s/dasil56 is illustrated in figure 6. this figure includes the sample/hold amplifier charac- teristics and assumes that the 'instrumentation amplifier is allowed to settle during the previous conversion. trtggeri r-.. sih control j } sih +fs e ' input .--'- , signal -fs -: , +fs ; sih output. - -i -fs -, 'nternal nnnn nnn cloci< j w w w ~t--i w w l- roc ~3s.' max i;~ ".' max idasi1'" s~ msb ==~lj ---,--, ~~ bltz j u blt3:==~j 8, " , i i r , i " i i bit 14 - - j 1>-1 ~ ilsa foft da51155i__- u fu//#t 1 s~, d' u' . bit " _u j (lsa for da511"'_-- notes w& " output data valid, . 2. this diagram assumes that tha instrumentation amplifier is allowed sufficient time to settle before the samplelhold amplifier is placed in the sample mode. instrumentation amplifier settling can take place during the aid conversion process for ihe next conversion (see throughput ratel. 3. the sfh control and trigger are tied together. pulse width must be 4..s (minll5..s (mini to allow the sfh amplifier to acquire the input signa" figure 6. das 1155/das 1156 timing diagram the trigger input and s/h control terminal can be tied together requiring only one conversion control signal. when the trigger pulse goes high, it places the sample/hold amplifier in the sample mode allowing it to acquire the present input signal. the trigger pulse must remain high for a minimum of 4i-ls/5j.ls, for the dasii55/dasii56 respectively1 to insure accuracy is attained. at the falling edge of the trigger pulse, the sample/ hold amplifier is placed in the hold mode, the a/d conversion da ta ar.nlj/sitlnn subsystems v.q.l. jl 1jj-19 :::- .....g - 1000 ..:...... ........... / = 10 ........ = 1 -- i' ....... ............ - "'" , -...:::::: , , , obsolete
begins, and all internallogie is reset. once the conversion process is initiated, it cannot be retriggered until after the end of conversion. with this negative edge of the trigger pulsc thc msb is set low with the remaining digital outputs set 10 logic high state, and the status line is set high and remains high thru the full conversion cycle. during conversion each bit, starting with the msb, is sequentially switched low at the rising edge of the internal clock. the internal dac output is then compared to the analog input and the bit decision is made. each comparison lasts one clock cycle with the complete 14-1l5-bit conversion taking 35f.ls/ 44f.ls maximum respectively for the dasi155/dasi156. at this time, the status line goes low signifving that the conversion is complete. for bus applications, the digital output can now be applied 10 the selected data bus bv enabling the tri-state buffers with the hi-enable and lo-enable ter- minals. gain and offset adjustments the dasi155/dasi156 each are provided with internal gain and offset adjustment potentiometers. each potentiometer has ample adjustment range so that gain and offset errors can be trimmed to zero. since offset calibration is not affected by changes in gain cali- bration, it should be performed first. proper gain and offset calibration require great care and the use of extremely sensitive and accurate reference instruments. the voltage standard used as a signal source must be very stable and be capable of being set to within :t iilolsb of the desired value at any point within its range. the analog input values given in tables i, ii, iii and in the following offset & gain calibration section, are values that should be present at the input to the internal adc. the value of the analog input will be affected by the gain of the input jnstrumentation amplifier.(example: for a full scale input of 0 to + 5v, divide the 0 to + loy range input values by 2 and set input gain to 2.) analog input oto + lov range dasllss daslls6 +9.99939v +9.99969v + s.ooooov + s.ooooov + i.2s000v + i.2s000v + 0.0006v + 0.0003v + o.oooov + o.oooov digital output binary c<>de daslls6 iii iii iii iii iii 100 000 000 000 000 001 000000 000 000 000 000 000 000 00 i 000 000 000 000 000 dasllss 11 iii iii iii iii i 0 000 000 000 000 00 i 00 000 000 000 00 000 000 000 00 i 00 000 000 000 000 table i. nominal unipolar/output relationships analog input :!: sv range +4.99939v + 2.s0000v +0.0006iv + o.ooooov - s.ooooov digital output offset binary code two's complement code illl1111111111o11l111i1j1111 ii 000 000 000 000 0 i 000 000 000 000 10000 000 000 001 00 000 000 000 001 i 0 000 000 000 000 00 000 000 000 000 00 000 000 000 000 i 0 000 000 000 000 table ii. dasl155 bipolar input/output relationships analog input :!: sv range + 4.99969v + 2.s0000v + 0.00030v + o.ooooov - s.ooooov digital output offset binary code two's complement code iii iii iii iii iii 011111 iii iii iii ii 0 000 000 000 000 0 i 0 000 000 000 000 i 00 000 000 000 00 i 000 000 000 000 00 1 i 00 000 000 000 000 000 000 000 000 000 000 000 000 000 000 1 00 000 000 000 000 table iii. dasl156 bipolar input/output relationships vol. ii, 15-20 data acquisition subsystems offset calibration for 0 to + joy unipolar range set the input voltage precisely to + 305f.ly for the dasi155 andf i 53,ly for the das1156. then adjust the zero potentiometcr until the converter is just on the verge of switching from 00 00 to ()()---uoi. for the -'- 5v bipolar range set the input voltage precisely to + 305f.l y for the das 1155 and + 153fl y for the das 1156. adjust the zero potentiometer until the offset binary coded units are just on the verge of switching from 00 00 10 00 01 and the two's complement coded units are just on the verge of switching from 10 00 to 10 0 i. gain calibration set the input voltage precisely \0 + 9.99909 (oasi155)/ +9.99954y (dasi156) for the 0 to + ioy units, or +4.99909y (dasi155)/ +4.99954v (dasi156) for :t 5v units. note that these values are i 1/2lsb less than nominal full scale. adjust the gain potentiometer until binary and offset binary coded units are just on the verge of switching from 11 10 to i i---nl i and two's complement coded units are just on the verge of switching from 011 10 to 011 11. throughput rate throughput rates for the dasi155/dasi156 can be increased by the use of the overlap mode, i.e. updating the input while the adc is making a conversion. the guaranteed throughput rates are 25khz ((i g = i, 20khz (ii. g = 1000 for the dasi155 and 20khz (il g = i and 1000 for the das 1156. when the ia settling time is less than or equal to the sum of sha acquisition time and adc conversion time, 39f.ls, the das throughput rate equals 1/39f.ls or 25.6khz. when ia settling time is greater than 39f.ls (see figure 5), the das throughput rate becomes dependent upon the ia settling time and equals its reciprocal. das1l55/das1l56 input/output relationships the dasi155/dasi156 produces a true binary coded output when configured as a unipolar device. configured as a bipolar device, it can produce either offset binary or two's complement output codes. the most significant bit (msb) is used to obtain the binary and offset binary code while the (msb) is used to obtain the two's complement code. table i shows the unipolar analog input/digital output dasi155/dasi156 relationships. tables ii and iii show the dasll55/dasll56 bipolar analog input/digital output relationships respectively. tri-state digital output the digital outputs are provided in parallel format to the output tri-state buffers. the output information can be applied to a data buss in either a one-byte or a two-byte format by using the hi-enable and la-enable terminals. if the tri-state feature is not required, normal digital outputs can be obtained by con- necting the enable pins to ground. power supply and grounding connections although the analog power ground and the digital ground are connected in the dasil55/dasil56, care must still be taken to provide proper grounding due to the high accuracy nature of the devices. though only general guidelines can be given, ground- ing should be arranged in such a manner as to avoid ground loops and to minimize the coupling of voltage drops (on the high current carrying logic supply ground) to the sensitive analog circuit sections. analog and digital grounds should remain sepa- rated on the pc board and terminated at the respective das ii 55/ dasi156 terminals. no power supply decoupling is required since, both the dasi155 and das 1156, contain high quality tantalum capacitors on each of the power supply inputs to ground. --- -- - obsolete
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